Wafer bond testing of semiconductor ICs is an increasingly important process. As circuit density increases and ICs become more complex, the potential for process variations and mistakes to occur increases. In particular, larger and more complex chips often have greater numbers of bond wires, leading to a greater risk of process problems in the wire bonding process. For example, FIG. 1 illustrates a typical IC 100 with dice 102, 103 stacked on a substrate 104 having bond pads 106, 108, 110, 112. The bond pads 106, 108, 110, 112 provide electrical connectivity between the IC 100 and the chip's pins (not shown), while bond wires 120-126 connect the die 102 to the bond pads 106-112 and bond wire 132 connects the die 103 to the bond pad 112. For the sake of clarity, other wire bonds are not shown. Typically, the bond wiring process results in each bond wire 120-126 being connected to a single bond pad 106-112. However, process mistakes can result in errors such as “opens,” where one bond wire 120-126 is not connected to its corresponding bond pad 106-112, e.g. bond wire 120, and “shorts” such as the one shown, where two or more bond wires 122-124 contact each other or are connected to the same bond pad 108, effectively shorting them out. Such errors result in incorrect data transfer to the die 102 and an IC that fails to function properly.
IC testing, such as wafer bond connectivity testing, is designed to detect such errors. However, current IC testing is not without its drawbacks. Greater circuit densities yield ICs with ever greater numbers of bond wires 120-126. Accordingly, many tests that check the connectivity of every single bond wire have become overly time-consuming and cost-ineffective. Conversely, tests that save time often sacrifice coverage to do so, or result in test data that can be difficult to analyze.
It is therefore desirable to improve the connectivity testing of ICs.